The increasing use of digital, generally clock-controlled signal-processing devices in various fields of application, particularly in motor vehicles, for the display or control of diverse functions requires a centralized or decentralized clock system, to which the individual clock-controlled devices are connected. As a result, interference signals are produced, directly or via the connected supply or signal lines, in a wide frequency range. The interference signals may propagate to nearby electronic devices or equipment via electric or electromagnetic interference fields and an unshielded supply network, and interfere with the operation of such devices or equipment. This interference is particularly disturbing if it affects analog subcircuits or analog signals. In motor vehicles, the audio equipment (broadcast receiver, mobile-radio unit, cassette player) is particularly affected, but interference may also be caused to analog sensors. The cause of the interference are the steep-edge current surges or spikes in the clock-controlled devices, which are initiated by one or both pulse edges of the system clock. These current spikes are produced by the activation of a great number of switching stages, e.g., by the charging or discharging of gate capacitances in MOS circuits. The higher the clock frequency, the faster the internal switching operations must be. This is achieved by a low-impedance circuit design, but the lower the circuit impedances, the higher the resulting current spikes will become. The number of switching stages to be activated, and thus the height of the current spikes, increases with increasing circuit complexity, particularly if the associated clock-controlled devices, e.g., processors, are implemented in CMOS technology. Buffering the very narrow load current spikes by external blocking capacitors is possible only imperfectly on cost grounds and because of the usual package designs for integrated circuits. With such blocking capacitors it is hardly possible to suppress the radio-frequency components of the interference signals.
Some methods are known in the art whereby a clock system can be modified to reduce interference to adjacent electronic equipment. Measures designed to provide passive shielding or reduce of the edge steepness of unnecessarily steep current spikes do not form part of the invention but can advantageously be combined with the latter and provide further interference suppression. The present invention relates to a random modulation of the system clock which distributes the energy content of the interference signal as evenly as possible over as wide a frequency range as possible. On a time average, the clock frequency should not deviate from a reference clock of fixed frequency.
Prior art patent DE 41 42 563 A1 discloses a clock generator which modulates the system clock by means of a phase/frequency modulator. The modulator is an electronically controlled leakage-current path which modulates the VCO control voltage, the controlled leakage current having a sawtooth, triangular, sinusoidal or other waveform. Whether phase or frequency modulation is effected depends on the design of the phase-locked loop and on the maximum amplitude of the leakage current.
In prior art patent application DE-A-44 23 074, clock-induced interference effects are reduced by switching the output signal from a clock generator between at least two division ratios by means of a frequency divider to obtain a clock signal which is stable in frequency. The switching of the frequency divider is effected by a pseudorandom-number generator. Prior art patent application DE-A-44 23 074 was withdrawn prior to publication.
U.S. Pat. No. 4,023,116 discloses a frequency synthesis system whose output clock is locked to a reference clock via a phase-locked loop. As the phase comparison is only possible during the pulse edges of the reference clock, the time interval between the pulse edges acts on the phase/frequency control as a "dead band". During the dead-band interval, the frequency synthesis system is unregulated, so that small, unregulated variations may occur in the period of the output signal as unwanted phase differences. The dead band is eliminated by means of suitable circuitry, thus reducing the frequency jitter of the synthesized output signal.
U.S. Pat. No. 4,933,890 discloses a clock-generating system in which the edges of a clock signal provided by a digitally controlled oscillator (=NVO) are phase-modulated by means of a binary random-number source, which assumes two output states in a random sequence, in order to reduce the harmonic content of the resulting clock signal.
Prior art patent EP 0 715 408 A1 discloses a clock-generating system in which the respective clock-pulse edges are modified in phase by means of an analog or discrete random-signal source and a variable delay device. The output of the random-signal source is either an analog random signal or a plurality of discrete random values, particularly a digital pseudorandom-number sequence.
The prior-art clock generators use methods in which the principal spectral lines of the noise spectrum are reduced by distributing their energy content among further spectral lines. Those methods in which the number of additional spectral lines is as high as possible with the deterministic interrelationship being as small as possible are particularly effective. Especially suited are those methods which employ random-signal sources. For the frequency or phase modulation of the clock signal by means of a random-signal source--it is particularly advantageous to phase-modulate the leading and trailing edges independently of each other, the magnitude of the phase deviation is important. The greater the noise bandwidth used for the phase modulation or the greater the number of different random numbers, the larger the phase deviation and the additional number of spectral lines can become. Thus, the amplitudes of the resulting noise spectrum are reduced as desired. In practice, however, a limitation is imposed since the random phase modulation of the system clock also changes the available pulse duration, pulse spacing, or mark/space ratio. At high clock frequencies, the mark and/or space interval may occasionally fall below the value predetermined by the respective circuit design and technology, in which case proper functioning of the circuit is no longer ensured.
It is therefore an object of the invention to improve a clock generator with random phase modulation of the system clock in such a way that it provides a system clock causing little electromagnetic interference, said system clock being distributed among as many spectral lines as possible without degrading the performance of the clock-controlled circuit by excessive phase deviation. According to the invention, this object is attained by a clock generator with the features claimed in claim 1. Further advantageous features are defined in the subclaims.